(1) Field of the Invention
The present invention relates to a bit synchronization circuit and a transmission system each for converting high speed burst signals to data trains in synchronization with a reference clock and, more particularly, to a bit synchronization circuit and a central terminal for a PON system each having an excellent phase variation tracking ability for high speed burst signals.
(2) Description of the Related Art
As an example of a transmission system for relaying burst signals transmitted from a plurality of terminal apparatus, there can be listed a PON system defined in ITU-T Recommendation G.983. 1 “Broadband Optical Access Systems based on Passive Optical Network (PON)” (Non-Patent Document 1). As shown in FIG. 2, the PON system is a point-to-multipoint optical transmission system having a structure in which each of optical fibers 11 (11-1 to 11-m) to be accommodated to a central terminals OLT (Optical Line Terminals) 1 (1A or 1B) is branched with an optical coupler (star coupler) 12 to a plurality of tributary optical fibers 13 (13-1 to 13-m) and remote terminals ONU (Optical Network Units) 10 (10-1 to 10-n) are connected to the individual tributary optical fibers.
In a PON section, a 53-byte ATM cell, e.g., is used for downstream data transmission from the central terminal 1 to each of the remote terminals 10 and a 56-byte cell obtained by adding a 3-byte overhead to the ATM cell, e.g., is used for upstream data transmission from the remote terminal 10 to the central terminal 1. The central terminal 1 generates downstream communication frames each with a frequency f0 in synchronization with a reference clock in the central terminal or with a multiple of the frequency f0. Each of the downstream communication frames has a transmission speed of, e.g., 622.08 Mbit/s and is composed of 224 consecutive cells. A control cell is inserted with a frequency of one control cell for every 27 cells. The control cell in the PON section is termed a PLOAM cell.
On the other hand, each of upstream communication frames has a transmission speed of about 100 Mbit/s to 155.52 Mbit/s, which is lower than the transmission speed of the downstream communication frame. For example, an upstream frame at 155.52 Mbit/s is composed of 53 cells and, as shown in FIG. 3, transfer cells B (B1-1, B1-2, . . . , Bn-1, Bn-2, . . . ) from the plurality of remote terminals 10-1 to 10-n are time-division multiplexed on the optical fiber 11-1.
Each of the remote terminals 10 extracts the reference clock from the downstream frame and transmits a cell (burst data set) B composed of a 3-byte overhead OH and a 53-byte payload (ATM cell portion) PLD to have a 56-byte length with a frequency f0 in synchronization with the reference clock. The transmission of the cell B is performed within a burst period (hereinafter referred to as the burst slot) Tb which is specified in the PLOAM cells by the central terminal 1 to each of the remote terminals 10. The period Tb of each the burst slots is on the order of several microseconds. The overhead OH is composed of a guard time GT with no signal, a preamble PR, and a delimiter DTL.
Since the length of the segment of the tributary optical fiber 13 branched from the optical splitter 12 is not uniform, the upstream cells (burst data sets) transmitted by the individual remote terminals reach the central terminal 1 to have phase differences, which are different from each other, with reference to the reference clock. Accordingly, the central terminal 1 is required to establish, upon reception of each burst data set, bit synchronization within the period during which the preamble PR composed of a series of alternating “1” and “0” bits is received, identify the leading portion of the payload by the subsequent delimiter DL, and perform a receiving process for the ATM cell.
As typical circuit technologies for the bit synchronization mentioned above, there have been known, e.g., a timing clock extracting method (Prior Art 1) which extracts a timing clock from received data by using a timing extracting circuit composed of a PLL (Phase Locked Loop) and a surface acoustic wave (SAW) filter and latches the received data based on the clock, an optimum phase clock selecting method (Prior Art 2) which preliminarily generates a plurality of internal clocks having different phases from a reference clock and performs a receiving process for that one of the internal clocks having a phase with the highest margin over the phase of received data, and an optimum phase data selecting method (Prior Art 3) which generates a plurality of data trains having different phases from received data and selecting that one of the data trains having the highest phase margin over a reference clock.
The bit synchronization circuit of the optimum phase clock selecting type (Prior Art 2) is shown by way of example in FIG. 4, which is composed of: an n-phase clock generator 41 for generating, from a reference clock CL having the same frequency as the received data, reference clocks having n phases each shifted from the adjacent one by a 1/n period; a multiphase data sampling unit 42 for latching the received data with the n-phase reference clocks and converting the latched received data to n-phase data trains having different phases; a phase determination unit 43 for performing a comparing process between those of the n-phase data trains outputted from the multiphase data sampling unit 42 which have adjacent phases to detect a variation point in the input data and generating a control signal for selecting the optimum phase clock having a phase with the highest margin over the phase of the received data; a clock selection unit 44 for selecting, in response to the control signal, the optimum phase clock from among the n-phase reference clocks; and a FIFO buffer 45 for temporarily storing the received data. The bit synchronization circuit is designed to write the received data in the FIFO buffer 45 in accordance with the optimum phase clock and read out the written data therefrom in accordance with the reference clock CL.
Examples of the foregoing bit synchronization circuit of optimum phase clock selecting type are disclosed in, e.g., Japanese Laid-Open Patent Publication No. 7-193562 (Patent Document 1), Japanese Laid-Open Patent Publication No. 9-181713 (Patent Document 2), Japanese Laid-Open Patent Publication No. 10-247903 (Patent Document 3), and Japanese Laid-Open Patent Publication No. 11-308204 (Patent Document 4).
The bit synchronization circuit of optimum phase data selecting type (Prior Art 3) is shown by way of example in FIG. 5, which is composed of: a multiphase data sampling unit 46 for converting received data to n-phase data trains each shifted in phase from the adjacent one by the 1/n period of a reference clock CL; a phase determination unit 47 for performing a comparing process between those of the n-phase data trains outputted from the multiphase data sampling unit 46 which have adjacent phases to detect a variation point in the input data and generating a control signal for selecting the optimum phase data train having the highest phase margin over the reference clock CL; an output data selection unit 48 for selectively outputting the optimum phase data train indicated by the control signal from among the n-phase data trains outputted from the multiphase data sampling unit 46; and an output data synchronization unit 49 for latching output data from the output data selection unit 48 in synchronization with the reference clock CL and outputting the latched data as a retimed data train.
Examples of the foregoing bit synchronization circuit of optimum phase data selecting type are disclosed in, e.g., Japanese Laid-Open Patent Publication No. 9-162853 (Patent Document 5) and Japanese Laid-Open Patent Publication No. 9-36849 (Patent Document 6).
Since the optical signal received by the central terminal 1 in the PON system attenuates while passing through the optical fiber and the level of the received optical signal is different from one transmitter (remote terminal) from another, a signal identification threshold is controlled variably on a per burst-data-set basis depending on the received light level of the preamble PR by using the ATC (Automatic Threshold Control) function of an O/E signal converter. As shown in FIG. 6, e.g., the optical signal of the preamble PR1 of a burst data set B1 is detected with an offset threshold TH0 and an ATC decision threshold TH1 for the burst data set B1 is set depending on the received light level of the preamble PR1. When the receiving process for the burst data set B1 is completed, the ATC decision threshold is reset to the offset threshold TH0 within the period of the guard time GT for the next burst data set so that the preamble PR2 of the next burst data set B2 is detected with the offset threshold.
In an optical transmission system, the level of an optical signal attenuates while passing through an optical fiber as a signal transmission medium so that an improvement in the responsivity of a unit for receiving the optical signal is required to elongate the distance of optical transmission. To set an optimum ATC decision threshold for a burst data set which is low in received optical power, it is necessary to minimize the value of the offset threshold TH0 which is set in the period of the guard time GT. As the offset threshold TH0 is reduced increasingly, however, an O/E signal converter becomes more sensitive to noise. As a result, an erroneous signal may be inputted to a bit synchronization circuit to cause the misoperation thereof.
To solve the problem, a method in which data received by a bit synchronization circuit is forcibly fixed to a logic value “0” by using a mask signal for a given period from the resetting of the ATC decision threshold till the reception of the next burst data set is proposed in, e.g., Japanese Laid-Open Patent Publication No. 10-327159 (Patent Document 7).
With an increase in the amount of traffic over a communication network, a PON system used for an access network is also required to be increased in transmission speed so that the standardization of a PON system having a transmission speed increased from the conventional 100 Mbit/s order to a Gbit/s class (hereinafter referred to as the G-PONs) has been promoted in, e.g., the ITU-T Recommendation G.984 or the IEEE Recommendation 802.3ah. In the G-PONs, an upstream data set transmitted from the remote terminal 10 to the central terminal 1 is composed of a variable-length burst data set, instead of a conventional fixed-length burst data set (ATM cell). Accordingly, the maximum burst length thereof may be elongated to about 1 ms, which is far larger than conventional several microseconds.
In the case of designing a bit synchronization circuit for a central terminal in the G-PON system having a higher transmission speed, however, the timing clock extracting method (Prior Art 1) which essentially takes a long time for clock extraction requires a long preamble segment for each of burst data sets, so that the transmission speed is lowered effectively. In the G-PON system, therefore, the optimum phase clock selecting method (Prior Art 2) or the optimum phase data selecting method (Prior Art 3) capable of achieving higher-speed bit synchronization is promising.
To enhance system flexibility in the G-PON system, it is necessary to give consideration to a system configuration in which data frequencies in upstream and downstream directions are asynchronous. It is also necessary to give consideration to a system configuration in which a data transfer speed in an upstream direction differs from one remote terminal to another, e.g., a system configuration in which burst data sets received from the individual remote terminals have varied frequencies f1 to fn relative to the reference clock frequency f0 of the central terminal 1.
In the conventional bit synchronization circuit of optimum phase clock selecting type or optimum phase data selecting type, once the optimum phase is determined during the period during which the preamble is received, the bit synchronization for the received data is performed without changing the optimum phase clock or the optimum phase data during the period during which the burst data set is received.
In the case of using the optimum phase clock selecting method or the optimum phase data selecting method in the G-PON bit synchronization circuit in which the burst data set has an increased length, however, there is a possibility that the optimum phase clock or the optimum phase data determined in the preamble region may come out of the optimum phase due to a phase variation or frequency asynchronization occurring in the payload region. In this case, retiming data based on the optimum phase clock or the optimum phase data determined in the preamble region becomes unstable and a bit error occurs in output data. Therefore, the bit synchronization circuit for the G-PON system is required to have a phase tracking ability over the entire region of the received burst data set.
In accordance with the optimum phase clock selecting method, however, it is not easy to control timing for clock switching in the payload region and suppress noise occurring upon the clock switching. On the other hand, the optimum phase data selecting method has a problem that, when the phase of the received data has varied by one period or more relative to the reference clock, data continuity is disturbed by the missing or overlapping of data upon the switching to the optimum phase data, which will be described later.